TSMC unveils advanced packaging breakthroughs and 2nm roadmap at symposium

TAIPEI: Taiwan Semiconductor Manufacturing Co (TSMC) showcased progress in its next-generation chipmaking and packaging technologies during the 2026 Taiwan Technology Symposium in Hsinchu on Thursday.

According to a report by Focus Taiwan, the company touted advances in its 2nm process and packaging solutions while highlighting its manufacturing roadmap for the next several years. Company executives unveiled the new A13, A12, and N2U process technologies and confirmed the mass production of a new chip-on-wafer-on-substrate (CoWoS) packaging solution, which the firm described as the largest in the world.

The announcement regarding production capabilities arrived as the semiconductor industry closely monitored yields from major foundry competitors. Yuan Li-pen, TSMC’s vice president for business development, said the 5.5-reticle-size CoWoS technology has achieved yields exceeding 98 per cent.

This update followed recent reports concerning developments at Intel and Samsung in the fields of advanced packaging and foundry services. According to the report, Intel’s EMIB-T packaging technology reached yield rates of approximately 90 per cent. Meanwhile, Samsung’s 2nm process yields were noted to have reached the mid-50-per cent range, placing the TSMC figures at the forefront of current industry benchmarks.

B.Z. Tien, TSMC vice president for operations and advanced technology engineering, addressed the company’s operational timeline and the necessary infrastructure to meet global demand for artificial intelligence and advanced nodes. To support this growth, the company scheduled the launch of five new fabrication plants within 2026.

The A13 and A12 processes are also scheduled for mass production in 2029, Yuan added. The report also mentioned that the company shared projections for future capacity, indicating a compound annual growth rate of 70 per cent for 2nm capacity between 2026 and 2028. Furthermore, the capacity for CoWoS and SoIC advanced packaging was expected to grow at an annual rate of more than 80 per cent through 2027.

Looking toward future high-performance computing needs, the report noted that Yuan said TSMC expects to begin production in 2028 of a 14-reticle-size CoWoS platform capable of integrating 20 high-bandwidth memory (HBM) chips. A larger version capable of integrating 24 HBM chips is slated for 2029.

Yuan noted that the 2nm node already saw significant adoption from the company’s customer base ahead of its full-scale implementation. According to Yuan, TSMC has already received about 25 finalized 2nm chip designs, with more than 70 additional customer projects currently in development. (ANI)